AMD launches Epyc 9005 “Turin” processors with up to 192 Zen 5c cores

AMD Launches 5th-Gen Epyc Server Processors “Turin”

In a nutshell: AMD has unveiled its fifth generation Epyc server processors, codenamed “Turin.” With 27 SKUs, these processors feature the new Zen 5 and 5c core architectures, positioning them to compete against Intel’s Granite Rapids and Sierra Forest offerings in the data center market.

The Epyc 9005 series, part of the 5th-gen Epyc CPU family, is compatible with AMD’s SP5 socket, similar to the Genoa and Bergamo processors based on Zen 4 architecture. This lineup introduces two designs – “Scale-Up” with 4nm Zen 5 cores for single-threaded performance, and “Scale-Out” with 3nm Zen 5c cores for multi-core throughput.

Leading the pack is the Epyc 9965 with 192 Zen 5c cores, 384 threads, base clock of 2.5GHz, boost clock up to 3.7GHz, 384MB L3 cache, and 500W TDP, priced at $14,813. The flagship Zen 5 product, Epyc 9755, offers 128 cores, 256 threads, 512MB L3 cache, 2.7GHz base clock, 4.1GHz boost clock, and 500W TDP, priced at $12,984.

At the entry-level, the Epyc 9015 features 8 Zen 5 cores, 3.6GHz base clock, 4.1GHz boost clock, 125W TDP, 64MB L3 cache, and an MSRP of $527.

AMD claims the Epyc 9965 outperforms the Xeon Platinum 8592+ by 3.7x in end-to-end AI workloads like TPCx-AI and offers 1.9x more throughput in generative AI models such as Meta’s Llama 3.1-8B.

The Zen 5 cores in Turin deliver significant performance gains over the previous generation, with up to 17% increase for Enterprise and Cloud platforms and up to 37% improvement for HPC and AI platforms.

The processors support boost frequencies up to 5GHz (Epyc 9575F and 9175F) and AVX-512 with a full 512-bit data path. The Epyc 9575F, designed for AI workloads, can handle up to 700,000 more inference tokens per second in a 1,000-node AI cluster due to its 5GHz boost clock.

Turin also introduces advancements like support for up to 12 channels of DDR5-6400 MT/s memory, 6TB memory capacities per socket, and 128 PCIe 5.0/CXL 2.0 lanes. Dynamic Post Package Repair (PPR) for x4 and x8 ECC RDIMMs enhances memory reliability.